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HCS193MS
September 1995
Radiation Hardened Synchronous 4-Bit Up/Down Counter
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW
P1 Q1 Q0 CPD CPU Q2 Q3 GND 1 2 3 4 5 6 7 8 16 VCC 15 P0 14 MR 13 TCD 12 TCU 11 PL 10 P2 9 P3
Features
* 3 Micron Radiation Hardened CMOS SOS * Total Dose 200K RAD (Si) * SEP Effective LET No Upsets: >100 MEV-cm2/mg * Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ) * Dose Rate Survivability: >1 x 1012 RAD (Si)/s * Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse * Latch-Up Free Under Any Conditions * Military Temperature Range: -55oC to +125oC * Significant Power Reduction Compared to LSTTL ICs * DC Operating Voltage Range: 4.5V to 5.5V * Input Logic Levels - VIL = 0.30% VCC Max - VIH = 0.70% VCC Min * Input Current Levels Ii 5A at VOL, VOH
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW
P1 Q1 Q0 CPD CPU Q2 Q3 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC P0 MR TCD TCU PL P2 P3
Description
The Intersil HCS193MS is a Radiation Hardened 4-bit binary UP/ DOWN synchronous counter. Presetting the counter to the number on the preset data inputs (P0 - P3) is accomplished by a low on the asynchronous parallel load input (PL). The counter is incremented on the low to high transition of the clock-up input (high on the clock-down), decremented on the low to high transition of the clock-down input (high on the clock-up). A high level on the MR input overrides any other input to clear the counter to zero. The Terminal Count Up goes low half a clock period before the zero count is reached and returns high at the maximum count. The HCS193MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.
Ordering Information
PART NUMBER HCS193DMSR HCS193KMSR HCS193D/Sample HCS193K/Sample HCS193HMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC +25oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 16 Lead SBDIP 16 Lead Ceramic Flatpack 16 Lead SBDIP 16 Lead Ceramic Flatpack Die DB NA
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
270
518759 3065.1
HCS193MS Functional Diagram
P0 15 P1 1 P2 10 P3 9
14 MR 11 PL 5 CPU PL R PQ FF0 CL Q PL R PQ FF1 CL Q PL R PQ FF2 CL Q PL R PQ FF3 TCU CL Q 13 TCD
12
4 CPD
8 GND 16 VCC
3 Q0 Q1
2 Q2
6 Q3
7
TRUTH TABLE FUNCTION Count Up Count Down Reset Load Preset Inputs H X X X X = Transition from low to high CLOCK UP CLOCK DOWN H RESET L L H L PARALLEL LOAD H H X L
H = High Level, L = Low Level, X = Immaterial,
Spec Number 271
518759
Specifications HCS193MS
Absolute Maximum Ratings
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical Performance Characteristics" are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . 100ns Max. Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2, 3 Output Current (Sink) IOL VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V 1 2, 3 Output Current (Source) IOH VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V VCC = 4.5V, VIH = 3.15V, IOL = 50A, VIL = 1.35V VCC = 5.5V, VIH = 3.85V, IOL = 50A, VIL = 1.65V Output Voltage High VOH VCC = 4.5V, VIH = 3.15V, IOL = -50A, VIL = 1.35V VCC = 5.5V, VIH = 3.85V, IOL = -50A, VIL = 1.65V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND 1 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC MIN 4.8 4.0 -4.8 -4.0 MAX 40 750 0.1 UNITS A A mA mA mA mA V
PARAMETER Quiescent Current
SYMBOL ICC
(NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND
Output Voltage Low
VOL
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
1, 2, 3
+25oC, +125oC, -55oC
VCC -0.1 VCC -0.1 -
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
V
1 2, 3
+25oC +125oC, -55oC +25oC, +125oC, -55oC
0.5 5.0 -
A A -
Noise Immunity Functional Test
FN
VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 2)
7, 8A, 8B
NOTES: 1. All voltages reference to device GND. 2. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 272
518759
Specifications HCS193MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9 10, 11 TPHL VCC = 4.5V 9 10, 11 CPU TO TCU TPLH, TPHL TPLH, TPHL TPLH VCC = 4.5V 9 10, 11 VCC = 4.5V 9 10, 11 VCC = 4.5V 9 10, 11 TPHL VCC = 4.5V 9 10, 11 PL to Qn TPLH VCC = 4.5V 9 10, 11 TPHL VCC = 4.5V 9 10, 11 MR to Qn TPHL, TPLH VCC = 4.5V 9 10, 11 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 MAX 31 38 31 36 23 27 23 27 32 39 31 37 26 31 34 40 33 38 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER CPU to Qn
SYMBOL TPLH
(NOTES 1, 2) CONDITIONS VCC = 4.5V
CPD TO TCD
CPD to Qn
NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) CONDITIONS VCC = 5.0V, f = 1MHz LIMITS TEMPERATURE +25oC +125oC, Input Capacitance CIN VCC = 5.0V, f = 1MHz -55oC MIN 16 24 0 0 16 24 MAX 53 75 10 10 15 22 25 17 UNITS pF pF pF pF ns ns MHz MHz ns ns ns ns ns ns
PARAMETER Capacitance Power Dissipation
SYMBOL CPD
+25oC +125oC, -55oC
Output Transition Time
TTHL TTLH FMAX
VCC = 4.5V
+25oC +125oC, -55oC
Maximum Operating Frequency (CPU, CPD) Setup Time Pn to PL
VCC = 4.5V
+25oC +125oC, -55oC
TSU
VCC = 4.5V
+25oC +125oC, -55oC
Hold Time Pn to PL
TH
VCC = 4.5V
+25oC +125oC, -55oC
Hold Time CPD to CPU or CPU to CPD
TH
VCC = 4.5V
+25oC +125oC, -55oC
Spec Number 273
518759
Specifications HCS193MS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) (NOTE 1) CONDITIONS VCC = 4.5V LIMITS TEMPERATURE +25oC +125oC Pulse Width PL TW VCC = 4.5V +25 C +125oC Pulse Width MR TW VCC = 4.5V +25 C +125 C Recovery Time PL to CPU, CPD TREC VCC = 4.5V +25oC +125o Recovery Time MR to CPU, CPD TREC VCC = 4.5V C
o o o
PARAMETER Pulse Width CPU to CPD
SYMBOL TW
MIN 20 30 16 24 20 30 16 24 5 5
MAX -
UNITS ns ns ns ns ns ns ns ns ns ns
+25oC +125oC
NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K RAD LIMITS TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN 4.0 -4.0 VCC -0.1 2 2 2 2 2 2 2 2 2 MAX 0.75 0.1 5 38 36 39 37 27 27 31 40 38 UNITS mA mA mA V V A ns ns ns ns ns ns ns ns ns
PARAMETER Quiescent Current Output Current (Sink) Output Current (Source) Output Voltage Low Output Voltage High Input Leakage Current Noise Immunity Functional Test CPU to Qn
SYMBOL ICC IOL IOH VOL VOH IIN FN TPLH TPHL
(NOTES 1, 2) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V VCC = 4.5V, VIN = VCC or GND, VOUT = VCC -0.4V VCC = 4.5V or 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOL = 50A VCC = 4.5V or 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOH = -50A VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 3) VCC = 4.5V VCC = 4.5V VCC = 4.5V VCC = 4.5V VCC = 4.5V VCC = 4.5V VCC = 4.5V VCC = 4.5V VCC = 4.5V
CPD to Qn
TPLH TPHL
CPU TO TCU CPD TO TCD PL to Qn
TPHL, TPLH TPHL, TPLH TPLH TPHL
MR to Qn
TPHL
NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. 3. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 274
518759
Specifications HCS193MS
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP 5 5
PARAMETER ICC IOL/IOH
DELTA LIMIT 12A -15% of 0 Hour
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 Sample/5005 Sample/5005 Sample/5005 Sample/5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 7, 9 Subgroups 1, 2, 3, 9, 10, 11, (Note 2) ICC, IOL/H READ AND RECORD ICC, IOL/H ICC, IOL/H ICC, IOL/H
NOTES: 1. Alternate Group A testing in accordance with method 5005 of MIL-STD-883 may be exercised. 2. Table 5 parameters only. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST METHOD 5005 PRE RAD 1, 7, 9 POST RAD Table 4 READ AND RECORD PRE RAD 1, 9 POST RAD Table 4 (Note 1)
NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V 0.5V VCC = 6V 0.5V 50kHz 25kHz
STATIC BURN-IN I TEST CONNECTIONS (Note 1) 2, 3, 6, 7, 12, 13 1, 4, 5, 8 - 11, 14, 15 16 -
STATIC BURN-IN II TEST CONNECTIONS (Note 1) 2, 3, 6, 7, 12, 13 8 1, 4, 5, 9 - 11, 14 - 16 -
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2) 1, 8 - 11, 14, 15 2, 3, 6, 7, 12, 13 4, 11, 16 5 -
NOTES: 1. Each pin except VCC and GND will have a resistor of 10K 5% for static burn-in. 2. Each pin except VCC and GND will have a resistor of 1K 5% for dynamic burn-in. TABLE 9. IRRADIATION TEST CONNECTIONS OPEN 2, 3, 6, 7, 12, 13 GROUND 8 VCC = 5V 0.5V 1, 4, 5, 9 - 11, 14 - 16
NOTE: Each pin except VCC and GND will have a resistor of 47K 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 275
518759
HCS193MS Intersil Space Level Product Flow - `MS'
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5)
NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 276
518759
HCS193MS AC Timing Diagrams
I/FMAX INPUT LEVEL CPU OR CPD INPUT LEVEL VS VS TW TPHL TPLH TPHL VS VS VS CPU OR CPD VS VS TPLH
QN
VS
VS
TCU OR TCD
FIGURE 1. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE WIDTH
FIGURE 2. CLOCK TO TERMINAL COUNT DELAYS
PN TW TW PL CPU OR CPD TPLH QN VS VS VS VS VS VS
INPUT LEVEL INPUT LEVEL VS TW TREC VS TPHL QN INPUT LEVEL CPU OR CPD TPHL VS TREC VS INPUT LEVEL VS
MR INPUT LEVEL
FIGURE 3. PARALLEL LOAD PULSE WIDTH, PARALLEL LOAD TO OUTPUT DELAYS, AND PARALLEL LOAD TO CLOCK RECOVERY TIME
FIGURE 4. MASTER RESET PULSE WIDTH, MASTER RESET TO OUTPUT DELAY AND MASTER RESET TO CLOCK RECOVERY TIME
PN TSU(H) TH PL
VS
VS TSU(L) TH VS VS
INPUT LEVEL
INPUT LEVEL
VOH
TTLH 80% 80%
TTHL
Q=p QN
Q=p
VOL
20%
OUTPUT
20%
FIGURE 5. SETUP AND HOLD TIMES DATA TO PARALLEL LOAD (PL)
FIGURE 6. OUTPUT TRANSITION TIME
AC Timing Diagrams
AC VOLTAGE LEVELS PARAMETER VCC VIH VS VIL GND HCS 4.50 4.50 2.25 0 0 UNITS V V V V V
AC Load Circuit
DUT TEST POINT CL RL
CL = 50pF RL = 500
Spec Number 277
518759
HCS193MS Die Characteristics
DIE DIMENSIONS: 104 x 86 mils 2642m x 2185m METALLIZATION: Type: AlSi Metal Thickness: 11kA 1kA GLASSIVATION: Type: SiO2 Thickness: 13kA 2.6kA WORST CASE CURRENT DENSITY: < 2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 mils x 4 mils
Metallization Mask Layout
HCS193MS
Q1 (2) P1 (1) VCC (16)
(15) P0 Q0(3)
(14) MR CPD(4)
(13) TCD
CPU(5)
(12) TCU Q2(6)
(11) PL
Q3(7)
(8) GND
(9) P3
(10) P2
Spec Number 278
518759

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